FAQ Management System - I'm trying to use SPI master capability of SMARC-T4378. HW setup 1. SMARC-T4378 2. EVK-STD-CARRIER with populated second ETH 3. oscilloscope monitoring at carrier board SPI0.0 SPI0.1 SPI1.0 SPI1.1 SW Many combination tried -The standard kernel from delivered SDCARD - Self build kernel from embedian GIT - it seems that SPI master is enable by default. McSPI is also enabled when I check with menuconfig - arago rootfs tar.gz downloaded from embedian. In user space I can see /dev/spidev2.0 /dev/spidev2.1 /dev/spidev3.0 /dev/spidev3.1 Write to this devices from C returns no error but I dont see any activity on EVM_STD_CARRIER SPI connectors. Comments, suggestion, remarks are welcome. Thanks in advance, Mirtcho Maglijanov

I'm trying to use SPI master capability of SMARC-T4378.
HW setup
1. SMARC-T4378
2. EVK-STD-CARRIER with populated second ETH
3. oscilloscope monitoring at carrier board SPI0.0 SPI0.1 SPI1.0 SPI1.1
SW
Many combination tried
-The standard kernel from delivered SDCARD
- Self build kernel from embedian GIT - it seems that SPI master is enable by default. McSPI is also enabled when I check with menuconfig
- arago rootfs tar.gz downloaded from embedian.

In user space I can see /dev/spidev2.0 /dev/spidev2.1 /dev/spidev3.0 /dev/spidev3.1

Write to this devices from C returns no error but I dont see any activity on EVM_STD_CARRIER SPI connectors.

Comments, suggestion, remarks are welcome.

Thanks in advance,
Mirtcho Maglijanov

Does somebody use the SPI ports of SMART437x?

Why In devicetree spi clock is defined as input while other signal CS/D0/D1 are defined for master?
0x1dc (PIN_INPUT | MUX_MODE4)

Last update:: 2016-08-05 17:36
Author:: Mirtcho Maglijanov
Revision:: 1.0

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