ARM11 based com

MXM-6410 Computer on Module

[edit] Introduction

This Chapter gives background information on the MXM-6410 computer on module products from Embedian.

Section include：

• MXM computer on Module Family
• Comparison of MXM series Computer on Module Family
• Block diagram
• Snapshots

[edit] MXM-6410 ARM1176JZF-S Based Computer on Module

MXM-6410 is a tiny and powerful Ethernet enable small module in world first MXM form factor. It is based on the new Samsung ARM1176JZF-S S3C6410 processor and runs at 533MHz that integrated Multi Format Codec (MFC) co-processor supports encoding and decoding of MPEG4/H.263/H.264 and decoding of VC1. This H/W Encoder/Decoder supports real-time video conferencing and TV out for both NTSC and PAL mode. Additional graphic 3D engine is a 3D Graphics Hardware Accelerator which can accelerate OpenGL ES 1.1 & 2.0 rendering. With small size (66mmx50mm) and very power saving (~2W), MXM-6410 features state of the art technology, aiming at low power systems that require high CPU performance and space critical application. Most importantly, all RISC-based modules will be pin-to-pin compatible from Embedian to save customers design efforts and extend their product lifetime.

MXM-6410 features state of the art technology, aiming at low power systems that require high CPU performance. They also provide all the interfaces needed in a modern embedded device. It includes TFT LCD interface, two USB host interface, Ethernet interface, four RS232 interface, Camera interface, CF interface, IDE interface, AC97 Audio Interface, IIC, PWM, TV-out and SPI through a 242-pin MXM golden finger connector as interface. MXM-6410 also includes a sophisticate power management mechanism. The small in size makes system integrators and manufacturers flexible in designing their product line with different shapes to make the products fast time to market. It can be applied to the general-purposed embedded application or multimedia-related embedded application by taking advantages of the MFC co-processor. With Linux and Windows CE 6.0 supported, users can easily migrate their original application from other platform or develop a new application on this platform.

A 242-pin golden finger connector enables the MXM-6410 series computer on module to interface with the OEM's custom circuitry, and with an evaluation carrier board that is supplied with Embedian's evaluation kit. The evaluation carrier board includes a LCD panel, headers and connectors for all interfaces.

[edit] MXM-6410 Series Block Diagram

The following diagram illustrates the system organization of the MXM-6410. Arrows indicate direction of control and not necessarily signal flow.

Figure 1.1 MXM-6410 Computer on Module Block Diagram

[edit] Snapshots

Figure 1.2 Snapshot of MXM-6410 Computer on Module

Details for this diagram will be explained in the following chapters.

[edit] Specifications

This Chapter contains specifications of MXM-6410 computer on module.

Section include：

• Functional specifications
• Mechanical specifications
• Electrical specifications
• Environmental specifications
• MTBF
• EMI/RFI and ESD protection

[edit] Functional Specification

Processor

• Samsung S3C6410
• ARM1176JZF-S core with Java acceleration engine and 16KB/16KB I/D Cache and 16KB/16KB I/D TCM
• Clock Rates up to 667Mhz (533Mhz is also available)
• 266Mhz 64/32-bit system bus architecture is composed of AXI, AHB and APB buses
• Multi Format Codec (co-processor) provides encoding and decoding of MPEG-4/H.263/H.264 up to 30fps@SD/D1 and decoding of VC1 video up to 30fps@SD/D1
• Manufactured using the 65nm process (Compared to earlier S3C6400 which is 90nm process)
• 2D graphics acceleration with BitBlit and rotation
• 3D graphics hardware accelerator which can accelerate OpenGL ES 1.1 & 2.0 rendering
• Vector Floating-Point (VFP) coprocessor support allowing efficient implementation of various encryption schemes as well as high quality 3D graphics applications

Power Supply

• Single input +5V DC power from 242-pin interface
• Power Saving Mode: Nomal, Suspend and Idle
• Real-time clock battery powered

Memory

• Onboard 128MB NAND Flash (Large Block)
• Onboard 128MB mDDR Memory (266Mhz 32-bit Connection, 256MB is available by project based)
• Independent 64MB mDDR Memory as video RAM (no need to share with system memory)
• CompactFlash(CF), Type I and Type II, 3.3V, True IDE Mode
• IDE (Shared with CF), ATA Standard support UDMA mode

Universal Serial Bus (USB)

• Chipset: CPU internal
• Two USB 1.1 host ports (12Mbit/s speed)
• OHCI Rev. 1.0 Compliance
• USB legacy keyboard, mouse and hard disk support

USB 2.0 Device

• Chipset: CPU internal
• One USB client 2.0 interface, supporting high speed as Device (480Mbps, on-chip transceiver)
• Compatible with USB specification version 2.0

COM Port

• Chipset: CPU internal
• Four RS232 Interfaces, TTL level
• Two of them are TX and RX only; And two of them are TX, RX, CTS and RTS

Ethernet

• Chipset：Davicom DM9000B
• One 10/100Mbps Ethernet (MAC integrated), RJ-45 connector onboard
• Compliance with IEEE 802.3u 100Base-TX and 802.3 10Base –T
• Compliance with IEEE 802.3u auto-negotiation protocol for automatic link-type selection
• Full-duplex/half -duplex capability
• Supports IEEE 802.3x full duplex flow control
• Support Auto-MDIX

CompactFlash(CF) Interface (Shared with IDE)

• Chipset: CPU CF Controller
• Type I and Type II, 3.3V
• Memory mode and True IDE mode
• Compatible with CF+ and CompactFlash Spec (Rev 3.0)

IDE Interface (Shared with CF)

• Chipset: CPU ATA Controller
• ATA UDMA mode

AC97 Audio-Codec Interface

• Chipset: CPU AC-link or IIS interface
• Support 16-bit Sample
• AC97 version 2.3 compliance interface
• 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs1-ch MIC input
• Advanced Linux Sound Architecture (ALSA) API support

Discrete I/O

• 12 general-purpose digital I/Os
• 8 External interrupt to eliminate performance hogging polling

IIC Interface

• Chipset: CPU internal
• 1-ch Multi-Master IIC-Bus
• Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode.

SPI Interface

• Chipset: CPU internal
• Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11
• 2x8 bits Shift register for Tx/Rx
• DMA-based or interrupt-based operation

Watchdog Timer (WDT)

• Chipset：CPU internal
• 16-bit Watchdog Timer
• Interrupt Request or System Reset at Timeout

CPU Video Graphic Array (VGA)

• Chipset：CPU LCD Controller
• TFT Panel Support
• Up to 1024x1024 resolutions (TBD)
• Independent 64MB DDR II memory as video RAM
• TTL (16-bit/24-bit) interface
• Support 5 Window Layer for PIP or OSD
• Programmable OSC window positioning
• 16-level alpha blending

Video Post Processor

• Chipset：CPU internal
• Video input format conversion
• Video/Graphic scaling up/down or zooming in/out
• Color space conversion from YCbCr to RGB and from RGB to YCbCr
• Dedicated scaler for TV Encoder

TV Out

• Chipset：CPU internal
• Support NTSC-M,J / PAL-B,D,G,H,I,M,Nc compliant video format
• Built in the MIE(Mobile Image Enhancer) Engine

Pulse Width Modulation (PWM)

• Chipset：CPU Internal
• 2-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation
• Programmable duty cycle, frequency, and polarity

Multi Format Codec (MFC)

• Chipset: CPU internal MFC co-processor
• MPEG-4 part-II simple profile encoding/decoding 30fps@SD/D1
• H.264/AVC baseline encoding/decoding 30fps@SD/D1
• H.263 profile3 encoding/decoding 30fps@SD/D1
• VC1 decoding 30fps@SD/D1
• Encoding tools

- [-16,+16] 1/2 and 1/4 pel accuracy motion estimation using the full-search algorithm

- Variable block sizes: 16x16, 16x8, 8x16 and 8x8

- Unrestricted motion vector

- MPEG-4 AC/DC prediction

- H.264/AVC intra-prediction (hardwired mode decision)

- In-loop deblocking filter for both H.264 and H.263 P3

- Error resilience tools

- MPEG-4 resync. Marker and data-partitioning with RVLC

- MPEG-4/AVC FMO

- Bit-rate control (CBR and VBR)

• Decoding tools

-Support all features of the standardsSupport NTSC-M,J / PAL-B,D,G,H,I,M,Nc compliant video format

JPEG Codec

• Chipset: CPU JPEG Codec co-processor
• Compression/decompression up to UXGA size
• Encoding format: YCbCr 4:2:2 / RGB565
• Decoding format: YCbCr 4:4:4/4:2:2/4:2:0 or gray

2D Graphic Accelerator

• Chipset: CPU internal
• Line/Point drawing, BitBLT and Color Expansion /Text Drawing

3D Graphic Accelerator

• Chipset: CPU internal
• 4M triangles/s @133MHz (Transform Only)
• 75.8M pixels/s fill-rates @133MHz (shaded pixels)
• Programmable Shader Model 3.0 support
• 128-bit (32-bit x 4) Floating-point Vertex Shader
• Geometry-texture cache support
• 128-bit (32-bit x 4) Floating-point two Fragment Shaders
• Max. 4K x 4K frame-buffer (16/32-bpp)
• 32-bit depth buffer (8-bit stencil/24-bit Z)
• Texture format: 1/2/4/8/16/32-bpp RGB, YUV 422, S3TC Compressed
• Support max. 8 surfaces (max. 8 user-defined textures)
• API Support: OpenGL ES 1.1 & 2.0, D3D Mobile
• Intelligent Host Interface

- 15 input data-types, Vertex Buffer & Vertex Cache

• H/W Clipping (Near & Far)
• 8-stage five-threaded Shader architecture
• Primitive assembly & hard-wired triangle setup engine
• One pixels/cycle hard-wired rasterizer
• One texturing engine (one bilinear-filtered texel/cycle each)
• Nearest/bilinear/trilinear filtering
• 8-layered multi-texturing support
• Fragment processing: Alpha/Stencil/Z/Dither/Mask/ROP
• Memory bandwidth optimization through hierarchical caching

- L1/L2 Texture-caches, Z/Color caches

Security Sub-System

• Chipset: CPU internal
• AES accelerator: ECB, CBC, CTR mode support
• DES/3DES accelerator: ECB, CBC mode support
• SHA-1 Hash engine
• H/W HMAC support
• Random Number Generator : PRNG 320-bit generation per 160 cycles
• FIFO-Rx/Tx: (two 32-word) for input and output streaming.
• DMA I/F to SDMA1(Security DMA 1)

Camera Interface

• Chipset: CPU internal
• ITU-R 601/ITU-R 656 format input support. 8-bit input is supported
• Both progressive and interlaced input are supported
• Camera input resolution up to 4096x4096 in YCbCr 4:2:2 format

- 4096x4096 input resolution assumes the hardware down-scaling units will be bypass

- Up to 2048x2048 input resolution can optionally be input to the hardware down-scaling unit

• Resolution down-scaling hardware support for input resolutions up to 2048x2048
• Codec/Preview output image generation (RGB 16/18/24-bit format and YCbCr 4:2:0/4:2:2 format)
• Image windowing and digital zoom-in function
• Image mirror and rotation supports Y-mirror, X-mirror, 90o, 180o and 270 o rotation
• H/W Color Space Conversion
• LCD controller direct path supported
• Image effect supported

Touch Panel or ADC Interface

• Chipset：CPU Internal ADC
• 10-bit CMOS ADC
• 4-wire ADC interface

System Bus Interface (ISA-like Interface)

• Chipset：CPU Card Bus
• For add-on companion chip
• 8-bit or 16-bit support

Real Time Clock (RTC)

• RTC power interface

JTAG

• Testing and debugging interface

BIOS

• U-Boot (Universal Bootloader)
• Ethernet TFTP download
• Booting from NAND Flash Technology

Operating System

• Linux 2.6.26.2 (Debian ARM Linux)
• Windows CE 6.0

[edit] Mechanical Specification

The MXM-6410 embedded ARM computer boards is very tiny (66mm x 50mm) in form factor. This section describes the component dimensions and mounting of the board. Detailed drawings are available from Embedian for production customers.

[edit] Dimensions

Length x Width: 66mm x 50mm (2.60" x 1.97")

[edit] Mechanical Drawing

The following mechanical drawing specifies the dimension of MXM-6410 computer on module, as well as key components on the board. All dimensions are in mini-meters.

Top View

Bottom View

[edit] Mounting Holes

Two mounting holes are provided for mounting. The diameter of the holes is 4.0 mm. (The diameter of the ring is 5.5mm.) Mounting holes are plated through and connected to the module ground plane.

For reliable ground connections, use locking washers (star or split) when securing an MXM-6410 computer on module in a carrier board. Make sure that the washers do not extend beyond the limits of the pads provided (5.5mm). A M3, F head, 4mm long, 5mm in diameter, and 1mm head thick screw is recommended.

[edit] Clearances

The MXM-6410 computer on module has a low profile. Key clearances are as follows:

Height on Top

Max 2.8 mm (110.24 mil)

Height on Bottom

Maximum 2.4 mm (94.49 mil)

Board Thickness

1.2 mm

Clearance over Top and Bottom

6.4 mm

[edit] Weight

About 20g

[edit] Electrical Specification

[edit] Supply Voltages

+5V DC power (+/- 5%)

MXM-6410 computer on module require a +5V power supply from custom carrier board.

[edit] Supply Voltage Ripple

100mV peak to peak 0 - 20MHz

[edit] Supply Current (Typical)

MXM-6410 series computer on module is a low power consumption computer on module. The power-consumption tests were executed to give an overview of the electrical conditions for several operational states.

Following table lists the typical power consumption of MXM-6410 computer on module. All I/Os are up under the testing environment.

Table 2.1 Power Consumption of MXM-6410 Computer on Module

Note:

1. The above data is module only and the tested LCD is 640x480 TFT panel.

[edit] Real-Time Clock (RTC) Battery

• Voltage range: 1.8V – 3.6V (Typical@3.0V)
• Quiescent current: max. 3uA@3.0 V

[edit] CF

• 3.3V only

[edit] LCD

The LCD signal control voltage specification is as follows.

• +3.3/5V for TTL level LCD Panel

[edit] Environmental Specification

[edit] Temperature

• Operating: -5^oC to +75^oC(*) (with appropriate airflow)
• Non-operating: -10^oC to +85^oC (non-condensing)

Note:

• (*) The maximum operating temperature is the maximum measurable temperature on any spot on the module's surface. You must maintain the temperature according to the above specification.

[edit] Humidity

• Operating: 0 to 95% (non-condensing)
• Non-operating: 0 to 95% (non-condensing)

[edit] MTBF

• System MTBF (hours) : >100,000 hours

The above MTBF (Mean Time Between Failure) values were calculated using a combination of manufacturer's test data, if the data was available, and a Bellcore calculation for the remaining parts. The Bellcore calculation used is "Method 1 Case 1". In that particular method the components are assumed to be operating at a 50 % stress level in a 40^o C ambient environment and the system is assumed to have not been burned in. Manufacturer's data has been used wherever possible. The manufacturer's data, when used, is specified at 50^oC, so in that sense the following results are slightly conservative. The MTBF values shown below are for a 40^oC in an office or telecommunications environment. Higher temperatures and other environmental stresses (extreme altitude, vibration, salt water exposure, etc.) lower MTBF values.

[edit] EMI/RFI and ESD Protection

The MXM-6410 computer on module incorporates a number of standard features that protect it from electrostatic discharge (ESD) and suppress electromagnetic and radio-frequency interference (EMI/RFI). Transient voltage suppressors, EMI fences, filters on I/O lines and termination of high-frequency signals are included standard on all systems.

The module provides surge protection on the input power lines of itself. This is especially important if the power supply wires will be subject to EMI/RFI or ESD. If the system incorporates other external boards, it is the responsibility of the designer or integrator to provide surge protection on the system input power lines.

[edit] Hardware Reference

This section gives details of the hardware pin out assignment of the MXM-6410 computer on module.

[edit] Connector Type

The MXM-6410 computer on module uses MXM 242-pin golden finder as interface. The connector on module is called header and the connector on custom board is called socket.

Figure 3.1 CN1 Socket connector Type (Mating Connector: B33P102-0013 (Speed Tech), AS0B326-S78N-7F (Foxconn) or compatible)

Figure 3.2 CN2 Header Type (On module, Connector: DF12-40DS-0.5V(**) (Hirose) or compatible)

Figure 3.3 CN2 Socket Type (On carrier board, Mating Connector : DF12(5.0)-40DP-0.5V(**) (Hirose) or compatible.)

[edit] Connector Mechanical Drawing

The detail connector mechanical drawing is as follows.

Figure 3.4 CN1 Socket Connector Mechanical Drawing

Figure 3.5 CN2 Header Connector Mechanical Drawing

Figure 3.6 CN2 Socket Connector Mechanical Drawing

[edit] Connector Location

MXM series computer on module use 242-pin MXM form factor golden finger connectors CN1 and a 40-pin board-to-board connector (DF12-40DS-0.5V (**) (Hirose) or compatible)CN2 as an interface to connect with carrier board. The CN2 is mainly for IDE UDMA mode or high speed modem related.

Figure 3.5 Connector Location I

Figure 3.6 Connector Location II

[edit] Connector Pin Assignments

The following tables describe the electrical signals available on the connectors of the MXM-6410 computer on module. Each section provides relevant details about the connector including part numbers, mating connectors, signal descriptions and references to related chapters. For precision measurements of the location of the connectors on the module, refer to section 2.2.2. for mechanical drawing.

Legend:

Signal Types:

[edit] CN1 Connector (Golden Finger)

Address bus, data bus, CompactFlash, LCD, TV out, JTAG, Ethernet, chip select signal, external interrupt signals and all other CPU related are from CN1.

The following table shows the pin outs of CN1 connector.

Table 3.1 CN1 Connector (Bottom Side)

Table 3.1	CN1 Connector (Bottom Side)
Description	Mating Connector : B33P102-0013 (Speed Tech), AS0B326-S78N-7F (Foxconn) or compatible
Header	Pin	Signal Name	Function	Type
	4-wire touch screen
1	XP	Plus X-axis on-off control signal	AI
3	XM	Minus X-axis on-off control signal	AI
5	YP	Plus Y-axis on-off control signal	AI
7	YM	Minus Y-axis on-off control signal	AI
ADC Input
9	AIN3	ADC Input	AI
11	AIN2	ADC Input	AI
13	AIN1	ADC Input	AI
15	AIN0	ADC Input	AI
Reserved Pin
17	RSVD	Reserved	NC
19	RSVD	Reserved	NC
21	RSVD	Reserved	NC
23	RTCK	TAP Controller Return Clock (For ARM11 JTAG)	O
Key
Key
Key
Key
Key
Key
37	RSVD	Reserved	NC
39	RSVD	Reserved	NC
DMA
41	DMAACK0	External DMA acknowledge	O
43	DMADREQ0	External DMA request	I
Address Bus
45	ADDR0	Address Bus	O
47	ADDR1	O
49	ADDR2	O
51	ADDR3	O
53	ADDR4	O
55	ADDR5	O
57	ADDR6	O
59	ADDR7	O
61	ADDR8	O
63	ADDR9	O
65	ADDR10	O
67	ADDR11	O
69	ADDR12	O
71	ADDR13	O
73	ADDR14	O
75	ADDR15	O
77	GND	Ground Power	P
Reserved Pin
79	RSVD	Reserved	NC
81	RSVD	NC
83	RSVD	NC
85	RSVD	NC
87	RSVD	NC
Extra Pins for 24-bit LCD Configuration
89	VD16	LCD data bus RED0(LSB)	O
91	VD17	LCD data bus RED1	O
93	VD8	LCD data bus GREEN0(LSB)	O
95	VD9	LCD data bus GREEN1	O
97	VD0	LCD data bus BLUE0(LSB)	O
99	VD1	LCD data bus BLUE1	O
CF ATA Mode Related
101	CD_ATA	CF Card Detection	I
103	INT_ATA	CF Interrupt request from ATA controller	I
105	RESET_ATA	CF CARD Reset	O
107	OE_ATA	CF Output enable strobe	O
109	WE_ATA	CF Write enable strobe	O
111	RSVD	Reserved	NC
113	ADRVALID	OneNAND Address Valid	O
115	GND	Ground	P
Chip Select
117	nGCS0	Chip Select	O
119	nGCS1	No Connect. Reversed for DM9000B	O
121	nGCS2	No Connect. Reversed for NAND FLASH	O
123	nGCS3	Chip Select	O
125	nGCS4	Chip Select	O
127	nGCS5	Chip Select	O
129	nWBE0	Write byte enable	O
131	nWBE1	O
133	nOE	Output Enable	O
135	nWE	Write Enable	O
Data Bus
137	DATA0	DATA[15:0] INPUT DATA DURING MEMORY READ AND OUTPUT DATA DURING MEMORY WRITE. BUS WIDTH OF 8/16 BIT IS PROGRAMMABLE	I/O
139	DATA1	I/O
141	DATA2	I/O
143	DATA3	I/O
145	DATA4	I/O
147	DATA5	I/O
149	DATA6	I/O
151	DATA7	I/O
153	DATA8	I/O
155	DATA9	I/O
157	DATA10	I/O
159	DATA11	I/O
161	DATA12	I/O
163	DATA13	I/O
165	DATA14	I/O
167	DATA15	I/O
169	nWAIT	nWAIT requests	I
171	CLKOUT	Clock Output	O
173	WAKEUP	Wakeup requests	I
175	nRESET_IN	Reset S3C6410	ST
177	nRESET_OUT	Reset External Device	O
Reserved Pin
179	RSVD	Reserved	NC
181	RSVD	NC
183	RSVD	NC
USB Host 1
185	USBH-	USB Host Data -	I/O
187	USBH+	USB Host Data +	I/O
Reserved Pin
189	RSVD	Reserved	NC
191	RSVD	NC
USB Host 2 (Can be configured as USB2.0 Client)
193	USBH-	USB Host Data -	I/O
195	USBH+	USB Host Data +	I/O
197	GND	Ground Power	P
USB 2 OTG Related Pins
199	USBVBUS	USB Mini-Receptacle Vbus	P
201	USBID	USB Mini-Receptacle Identifier	I
203	USBDRWBUS	Drive Vbus for Off-Chip Charge Pump	O
205	RSVD	Reserved	NC
Boot Selection
207	XSELNAND	Select Flash Memory	I
209	OM1	Operation mode selection	I
211	OM2	Operation mode selection	I
213	OM3	Operation mode selection	I
215	OM4	Operation mode selection	I
Camera Interface
217	XCICLK	Master Clock to the Camera processor	O
219	XCIHREF	Horizontal Sync, driven by the Camera processor	I
221	XCIPCLK	Pixel Clock, driven by the Camera processor	I
223	XCInRST	Software Reset to the Camera processor	O
225	XCISYNC	Vertical Sync, driven by the Camera processor	I
227	XCIYDATA0	Pixel Data, driven by the Camera processor	I
229	XCIYDATA1	Pixel Data, driven by the Camera processor	I
231	XCIYDATA2	Pixel Data, driven by the Camera processor	I
233	XCIYDATA3	Pixel Data, driven by the Camera processor	I
235	XCIYDATA4	Pixel Data, driven by the Camera processor	I
237	XCIYDATA5	Pixel Data, driven by the Camera processor	I
239	XCIYDATA6	Pixel Data, driven by the Camera processor	I
241	XCIYDATA7	Pixel Data, driven by the Camera processor	I

Table 3.2 CN1 Connector (Top Side)

Table 3.2	CN1 Connector (Top Side)
Description	Mating Connector : B33P102-0013 (Speed Tech), AS0B326-S78N-7F (Foxconn) or compatible
Header	Pin	Signal Name	Function	Type
	TV Out
2	DACOUT0	TV-Out	AO
4	DACOUT1	TV-Out	AO
JTAG
6	TMS	TAP Controller Mode Select	I
8	TDO	TAP Controller Data Output	O
10	TDI	TAP Controller Data Input	I
12	TCK	TAP Controller Clock	I
14	nTRST	TAP Controller Reset	I
AC97
16	AC_SYNC	48kHz fixed rate sample sync.	O
18	AC_BIT_CLK	12.288MHz serial data clock	IO
20	AC_nRESET	AC'97 Master H/W Reset	O
22	AC_SDATA_IN	AC'97 input stream	I
24	AC_SDATA_OUT	AC'97 output stream	O
Key
Key
Key
Key
Key
Key
Power Input
38	EXT5V	DC in 5V	P
40	EXT5V	DC in 5V	P
42	EXT5V	DC in 5V	P
44	EXT5V	DC in 5V	P
CPU LCD
46	VD18	LCD data bus RED2	O
48	VD19	LCD data bus RED3	O
50	VD20	LCD data bus RED4	O
52	VD21	LCD data bus RED5	O
54	VD22	LCD data bus RED6	O
56	VD23	LCD data bus RED7 (MSB)	O
58	VD10	LCD data bus GREEN2	O
60	VD11	LCD data bus GREEN3	O
62	VD12	LCD data bus GREEN4	O
64	VD13	LCD data bus GREEN5	O
66	VD14	LCD data bus GREEN6	O
68	VD15	LCD data bus GREEN7 (MSB)	O
70	VD2	LCD data bus BLUE2	O
72	VD3	LCD data bus BLUE3	O
74	VD4	LCD data bus BLUE4	O
76	VD5	LCD data bus BLUE5	O
78	VD6	LCD data bus BLUE6	O
80	VD7	LCD data bus BLUE7 (MSB)	O
82	VCLK	LCD clock signal	O
84	HSYNC	Horizontal synchronous signal	O
86	VSYNC	Vertical synchronous signal	O
88	VDEN	Data enable signal	O
90	GND	Grpund Power	P
PWM
92	PWM0	Pulse Width Modulation Output	O
94	PWM1	O
Reserved Pin
96	RSVD	Reserved	NC
98	RSVD	Reserved	NC
IIC
100	IICSCL	IIC-bus clock	IO
102	IICSDA	IIC-bus data	IO
SPI
104	SPIMISO0	Master mode: data input; Slave mode: data output	IO
106	SPIMOSI0	Master mode: data output; Slave mode: data input	IO
108	SPICLK0	SPI Clock	IO
110	nSS0	SPI Chip Select	I
112	SPIMISO1	Master mode: data input; Slave mode: data output	IO
114	SPIMOSI1	Master mode: data output; Slave mode: data input	IO
116	SPICLK1	SPI Clock	IO
118	nSS1	SPI Chip Select	I
Interrupt
120	EXT_INT1	External interrupt request	I
122	EXT_INT2	I
124	EXT_INT3	I
126	EXT_INT4	I
128	EXT_INT5	I
130	EXT_INT6	I
132	EXT_INT7	I
134	EXT_INT8	I
136	GND	Ground Power	I
GPIOs
138	GPIO1	General input/output ports	IO
140	GPIO2	IO
142	GPIO3	IO
144	GPIO4	IO
146	GPIO5	IO
148	GPIO6	IO
150	GPIO7	IO
152	GPIO8	IO
154	GPIO9	IO
156	GPIO10	IO
158	GPIO11	IO
160	GPIO12	IO
162	VCCIO_PWREN	External Device Power Control	O
164	VCCLCD_PWREN	Panel Power Control	O
166	BACKLIGHT_EN	Panel Backlight Control	O
168	LCD_PWREN	Panel Signal Control	O
170	BBAT	RTC Battery Power(DC 3V)	P
SD Card(*)
172	SD_nCD	SD Insert Detect	I
174	SD_WP	SD Write Protect	I
176	SDCLK	SD Clock	O
178	SDCMD	SD receive response/ transmit command	O
180	SDDAT0	SD receive/transmit data	IO
182	SDDAT1	SD receive/transmit data	IO
184	SDDAT2	SD receive/transmit data	IO
186	SDDAT3	SD receive/transmit data	IO
188	GND	Ground Power	P
UART3
190	RXD3	UART receives data input	I
192	TXD3	UART transmits data output	O
Reserved Pin
194	RSVD	Reserved	NC
196	RSVD	NC
198	RSVD	NC
200	RSVD	NC
202	RSVD	NC
204	RSVD	NC
UART0~2
206	RXD2	UART receives data input	I
208	TXD2	UART transmits data output	O
210	nCTS1	UART clear to send input signal	I
212	nRTS1	UART request to send output signal	O
214	RXD1	UART receives data input	I
216	TXD1	UART transmits data output	O
218	nCTS0	UART clear to send input signal	I
220	nRTS0	UART request to send output signal	O
222	RXD0	UART receives data input	I
224	TXD0	UART transmits data output	O
Ethernet
226	LANLED1	Ethernet Speed LED	O
228	LANLED2	Ethernet Link LED	O
230	AVDD18	1.8V For Transformer	P
232	TX-	Ethernet Transmits data-	O
234	TX+	Ethernet Transmits data+	O
236	AGND	Ethernet Ground	P
238	RX-	Ethernet Receives data-	I
240	RX+	Ethernet Receives data+	I
242	AVDD18	1.8V For Transformer	P

(*)As of now, Linux driver is not supported.

(**)SSP can also be congigured as SPI by software.

[edit] CN2 Connector (For IDE UDMA mode or high speed modem only)

MXM-6410 has a dedicated IDE UDMA mode interface (can be configured as high speed modem) from CN2. If your device is not using the IDE ATA hard drive or high speed modem, users can skip this part.

The following table shows the pin outs of CN2 connector.

Table 3.3 CN2 Connector

Table 3.3	CN2 Connector
Description	DF12-40DS-0.5V (**) (Hirose) or compatible Mating Connector : DF12(5.0)-40DP-0.5V (**) (Hirose) or compatible.
Header	Pin	Signal Name	Function	Type
	1(*)	XHIADR0	Address bus, driven by the Modem chip	I
2	XHIDATA0	Data bus, driven by the Modem chip	IO
3	XHIADR1	Address bus, driven by the Modem chip	I
4	XHIDATA1	Data bus, driven by the Modem chip	IO
5	XHIADR2	Address bus, driven by the Modem chip	I
6	XHIDATA2	Data bus, driven by the Modem chip	IO
7	XHIADR3	Address bus, driven by the Modem chip	I
8	XHIDATA3	Data bus, driven by the Modem chip	IO
9	XHIADR4	Address bus, driven by the Modem chip	I
10	XHIDATA4	Data bus, driven by the Modem chip	IO
11	XHIADR5	Address bus, driven by the Modem chip	I
12	XHIDATA5	Data bus, driven by the Modem chip	IO
13	XHIADR6	Address bus, driven by the Modem chip	I
14	XHIDATA6	Data bus, driven by the Modem chip	IO
15	XHIADR7	Address bus, driven by the Modem chip	I
16	XHIDATA7	Data bus, driven by the Modem chip	IO
17	XHIADR8	Address bus, driven by the Modem chip	I
18	XHIDATA8	Data bus, driven by the Modem chip	IO
19	XHIADR9	Address bus, driven by the Modem chip	I
20	XHIDATA9	Data bus, driven by the Modem chip	IO
21	XHIADR10	Address bus, driven by the Modem chip	I
22	XHIDATA10	Data bus, driven by the Modem chip	IO
23	XHIADR11	Address bus, driven by the Modem chip	I
24	XHIDATA11	Data bus, driven by the Modem chip	IO
25	XHIADR12	Address bus, driven by the Modem chip	I
26	XHIDATA12	Data bus, driven by the Modem chip	IO
27	XHInCS	Chip select, driven by the Modem chip	I
28	XHIDATA13	Data bus, driven by the Modem chip	IO
29	XHInCS_MAIN	Chip select for LCD bypass main, driven by the Modem chip	I
30	XHIDATA14	Data bus, driven by the Modem chip	IO
31	XHInCS_SUB	Chip select for LCD bypass sub, driven by the Modem chip	I
32	XHIDATA15	Data bus, driven by the Modem chip	IO
33	XHInWE	Write enable, driven by the Modem chip	I
34	XHIDATA16	Matrix Key Returns	IO
35	XHInOE	Read enable, driven by the Modem chip	I
36	XHIDATA17	Matrix Key Returns	IO
37	XHInIRQ	Interrupt request to the Modem chip	O
38	RSVD	Reserved	NC
39	GND	Ground Power	P
40	GND	Ground Power	P

(*) For pins marked as yellow are IDE UDMA mode related pins. For more details, please refer to the carrier board reference schematics in evaluation kit.

The default software configuration of CN2 is set to be IDE UDMA mode. However, those pins in CN2 can also be configured as high speed modem or GPIOs. For details, interested users can refer to the Port K, Port L and Port M control registers in S3C6410 CPU manual.

[edit] Firmware Architecture

The firmware means the software that stores in NAND flash. MXM-6410 computer on module support boot from NAND flash directly. However, the evaluation kit has a NOR flash to help user restore the firmware in NAND flash. People can refer to Dual BIOS Design section for more details.

For Linux, the firmware in NAND includes u-boot, sysconfig, kernel zImage and rescue root filesystems (initrd). And for Windows CE, the firmwares in NAND includes u-boot and NK.nb0.

This chapter explains the firmware architecture of NAND flash for both opearting sytem and how to update them.

[edit] Firmware for Linux

Figure 4.1 shows the firmware architecture of Linux in NAND.

Figure 4.1 Firmware Architecture of Linux in NAND Flash

The u-boot starts from the 0th block.(0x0, 1 block = 16K). The Linux kernel zImage starts from the 12th block. (0xc) The sysconfig stores the system configuruation like IP address, default drivers to be load, default services,,,,.etc. and starts from the 128th block. (0x80) The rescue file system is a small file system for rescue purposed and load the minimum set drivers and starts from the 256th block. (0x100) There are about 44MB unsed in NAND for users.

Users need a CF card or hard drive with root file system installed to boot up the complete system. (Users can also build his own smaller root filesystems.) The will be described at Backup and Restore Root File Systems section.

Users can update the firmware under u-boot or Linux root filesystems. The Embedian factory default is fimware pre-installed. Unless necessary, Embedian doesn't recommend you update firmware since the system might not boot anymore if you did wrong operation. (If you develop your own u-boot and kernel, you will need to do that.) There are two ways to update firmware. Following tells howto.

[edit] Update firmware under u-boot

You can update firmware under u-boot command prompt using Ethernet tftp download. Please be careful expecially when update u-boot itself or the system might not boot anymore. In case that the u-boot is gone, please go to next chapter and use NOR boot to restore the u-boot.

Before doing that, you need a tftp server program (there are many open source tftp server that you can use.) and install the tftp server under your Windows or Linux host PC. Please put the uboot.bin, zImage.dat, sysconfig.img and nand.img files (they are file name of u-boot, kernel zImage, sysconfig and initrd respectyively.) under tftp root directory.

Then go to u-boot command prompt. To do that, press any key when booting.

We recommend you erase the firmware in NAND first.

# nande 0xc 0x2000000

This will erase the firmware in NAND except u-boot.

If you want to erase all firmwares including of u-boot, you can

# nande 0x0 0x2000000

Now you have erase the u-boot, kernel zImage, sysconfig and initrd.

Next, ou need set up the IP address of your tftp server and device first.

# setenv ipaddr xxx.xxx.xxx.xxx

# setenv serverip xxx.xxx.xxx.xxx

# saveenv

For Example:

ipaddr 192.168.1.2

serverip 192.168.1.121

Note:

• Make sure that the ipaddr for device and serverip for Windows (or Linux) PC are in the same network domain.

Next, you can update the uboot.bin, zImage.dat, sysconfig.img and nand.img.

# tftp 30000000 uboot.bin

# nandw 0x0 0x1c000 30000000

# tftp 30000000 zImage.dat

# nandw 0xc 0x190000 30000000

# tftp 30000000 sysconfig.img

# nandw 0x80 0x200000 30000000

# tftp 30000000 nand.img

# nandw 0x100 0x1000000 30000000

Reboot, and now you have your firmware update.

[edit] Update firmware under Linux root file systems

You can also use Linux "dd" command at root file system. You need a CF card or hard drive with root file system installed and plug into devices. Copy the u-boot.bin, zImage and initrd.img (They are the file name of u-boot, kernel zImage and initrd.) into / directory. (You can ftp the files to devices.)

[root@apc7110 /]# cd /

[root@apc7110 /]# dd if=/u-boot.bin of=/dev/mtdblock/0

[root@apc7110 /]# dd if=/zImage of=/dev/mtdblock/2

[root@apc7110 /]# dd if=/initrd.img of=/dev/mtdblock/4

Reboot, and you have firmwares update.

[edit] Firmware for Windows CE 5.0

Figure 4.2 Firmware Architecture in NAND for Windows CE

Most Windows CE device using eboot as bootloader. Embedian uses u-boot still since u-boot is moch more powerful than eboot.

There are only two files (u-boot and Nk.nb0) in NAND flash. The u-boot starts from the 0th block.(0x0, 1 block = 16K). The NK.nb0 starts from the 12th block. (0xc) There are about 32MB unsed in NAND for users.

Users can update the firmware under u-boot. The Embedian factory default is fimware pre-installed. Unless necessary, Embedian doesn't recommend you update firmware since the system might not boot anymore if you did wrong operation. (If you develop your own u-boot and Nk.nb0, you will need to do that.) Following tells you how to update firmware under Windows CE system.

[edit] Update firmware under u-boot

You can update firmware under u-boot command prompt using Ethernet tftp download. Please be careful expecially when update u-boot itself or the system might not boot anymore. In case that the u-boot is gone, please go to next chapter and use NOR boot to restore the u-boot.

Before doing that, you need a tftp server program (there are many open source tftp server that you can use.) and install the tftp server under your Windows or Linux host PC. Please put the uboot.bin, zImage.dat, sysconfig.img and nand.img files (they are file name of u-boot, kernel zImage, sysconfig and initrd respectyively.) under tftp root directory.

Then go to u-boot command prompt. To do that, press any key when booting.

We recommend you erase the firmware in NAND first.

# nande 0xc 0x2000000

This will erase the firmware in NAND except u-boot.

If you want to erase all firmwares including of u-boot, you can

# nande 0x0 0x2000000

Now you have erase the u-boot, kernel zImage, sysconfig and initrd.

Next, ou need set up the IP address of your tftp server and device first.

# setenv ipaddr xxx.xxx.xxx.xxx

# setenv serverip xxx.xxx.xxx.xxx

# saveenv

For Example:

ipaddr 192.168.1.2

serverip 192.168.1.121

Note:

• Make sure that the ipaddr for device and serverip for Windows (or Linux) PC are in the same network domain.

Next, you can update the uboot.bin, Nk.nb0.

# tftp 30000000 uboot.bin

# nandw 0x0 0x1c000 30000000

# tftp 30000000 Nk.nb0

# nandw 0xc 0x2000000 30000000

Reboot, and you have your firmware update.

[edit] General PCB Design Recommendations

This section gives general description of the design recommendation of the Printed Circuit Board (PCB) for MXM-6410 computer on module carrier boards. From a cost- effectiveness point of view, a four-layer board is the target platform for the carrier board design. For better quality, a six-layer or eight-layer board is preferred.

[edit] Nominal Board Stack Ups

The trace impedance typically noted (55 Ω ± 10%) is the "nominal" trace impedance for a 5-mil wide external trace and a 4-mil wide internal trace. However, some stackups may lead to narrower or wider traces on internal or external layers in order to meet the 55-Ω impedance target, that is, the impedance of the trace when not subjected to the fields created by changing current in neighboring traces. Note the trace impedance target assumes that the trace is not subjected to the EMI fields created by changing current in neighboring traces.

It is important to consider the minimum and maximum impedance of a trace based on the switching of neighboring traces when calculating flight times. Using wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce settling time. Coupling between two traces is a function of the coupled length, the distance separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the effects of trace-to-trace coupling, the routing guidelines documented in this Section should be followed. Also, all high speed, impedance controlled signals should have continuous GND referenced planes and cannot be routed over or under power/GND plane splits.

[edit] Four Layer Board Stackup

Figure 5-1 illustrates an example of a four-layer stack-up with 2 signal layers and 2 power planes. The two power planes are the power layer and the ground layer. The layer sequence of component-ground-power-solder is the most common stack-up arrangement from top to bottom.

Figure 5.1 Four-Layer Stack-Up

Table 5.1 Recommended Four-Layer Stack-Up Dimensions

Note:

Target PCB Thickness totals 62mil+/-10%

[edit] Six Layer Board Stack Up

Figure 5-2 illustrates an example of a six-layer stack-up with 4 signal layers and 2 power planes.

The two power planes are the power layer and the ground layer. The layer sequence of component-ground-IN1-IN2-power-solder is the most common stack-up arrangement from top to bottom.

Figure 5.2 Six-Layer Stack-Up

Table 5.2 Recommended Six-Layer Stack-Up Dimensions

Note:

Target PCB Thickness totals 62mil+/-10%

[edit] Differential Impedance Targets for Microstrip Routing

Table 5.3 shows the target impedance of the differential signals. The carrier board should follow the required impedance in this table.

Table 5.3 Differential Signals Impedance Requirement

[edit] Alternative Stack Ups

When customers choose to use different stack-ups (number of layers, thickness, trace width, etc.), the following key elements should be observed:

1. Final post lamination, post etching, and post plating dimensions should be used for electrical model extractions.
2. All high-speed signals should reference solid ground planes through the length of their routing and should not cross plane splits. To guarantee this, both planes surrounding strip-lines should be GND.
3. Recommend that high-speed signal routing be done on internal, strip-line layers. High-speed routing on external layers should be minimized in order to avoid EMI. Routing on external layers also introduces different delays compared to internal layers. This makes it extremely difficult to do length matching if routing is done on both internal and external layers.

[edit] Carrier Board Design Guidelines

This section gives detail description of the design recommendation of the MXM-6410 computer on module carrier boards. It points out the rules that need to be carefully followed in circuit design and layout.

[edit] General Circuit Design Guide

This section states the circuit design guide. Please follow carefully or the system might not able to boot.

[edit] System-Wise

Please contact Embedian for this part.

[edit] Universal Serial BUS (USB)

MXM-6410 computer modules provide two USB 1.1 ports.

[edit] Universal Serial Bus (USB)

The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial interface for adding external peripheral devices such as game controllers, communication devices and input devices on a single bus.

USB stands for Universal Serial Bus, an industry-standard specification for attaching peripherals to a computer. It delivers high performance, the ability to plug in and unplug devices while the computer is running, great expandability, and a wide variety of solutions.

[edit] Signal Description

Table 6.1